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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. a 02/07/03 IS62WV51216ALL is62wv51216bll issi ? copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtai n the latest version of this device specification before relying on any published information and before placing orders for products. 512k x 16 low voltage, ultra low power cmos static ram features ? high-speed access time: 45ns, 55ns, 70ns cmos low power operation ? 36 mw (typical) operating ? 12 w (typical) cmos standby ttl compatible interface levels single power supply ? 1.65v--2.2v v dd (62wv51216all) ? 2.5v--3.6v v dd (62wv51216bll) fully static operation: no clock or refresh required three state outputs data control for upper and lower bytes industrial temperature available description the issi IS62WV51216ALL/ is62wv51216bll are high- speed, 8m bit static rams organized as 512k words by 16 bits. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high- performance and low power consumption devices. when cs1 is high (deselected) or when cs2 is low (deselected) or when cs1 is low, cs2 is high and both lb and ub are high, the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable (we) controls both writing and reading of the memory. a data byte allows upper byte (ub) and lower byte ( lb) access. the IS62WV51216ALL and is62wv51216bll are packaged in the jedec standard 48-pin mini bga (7.2mm x 8.7mm) and 44-pin tsop (type ii). functional block diagram february 2003 a0-a18 cs1 oe we 512k x 16 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb cs2
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? pin configurations 48-pin mini bga (7.2mm x 8.7mm) pin descriptions a0-a18 address inputs i/o0-i/o15 data inputs/outputs cs1 , cs2 chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v dd power gnd ground 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 cs2 i/o 8 ub a3 a4 cs1 i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 a17 a7 i/o 3 v dd` v dd i/o 12 gnd a16 i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 a18 a8 a9 a10 a11 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 cs1 i/o0 i/o1 i/o2 i/o3 v dd gnd i/o4 i/o5 i/o6 i/o7 we a16 a15 a14 a13 a12 a5 a6 a7 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd v dd i/o11 i/o10 i/o9 i/o8 a18 a8 a9 a10 a11 a17 44-pin tsop (type ii)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? truth table i/o pin mode we we we we we cs1 cs1 cs1 cs1 cs1 cs2 oe oe oe oe oe lb lb lb lb lb ub ub ub ub ub i/o0-i/o7 i/o8-i/o15 v dd current not selected x h x x x x high-z high-z i sb 1 , i sb 2 x x l x x x high-z high-z i sb 1 , i sb 2 xxxxhh high-z high-z i sb 1 , i sb 2 output disabled h l h h l x high-z high-z i cc h l h h x l high-z high-z i cc read h l h l l h d out high-z i cc h l h l h l high-z d out hlhlll d out d out write l l h x l h d in high-z i cc l l h x h l high-z d in llhxll d in d in operating range (v dd ) range ambient temperature IS62WV51216ALL (70ns) is62wv51216bll (55ns, 70ns) is62wv51216bll (45ns) commercial 0c to +70c 1.65v - 2.2v 2.5v - 3.6v 3.0 - 3.6v industrial ?40c to +85c 1.65v - 2.2v 2.5v - 3.6v
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? dc electrical characteristics (over operating range) symbol parameter test conditions v dd min. max. unit v oh output high voltage i oh = -0.1 ma 1.65-2.2v 1.4 ? v i oh = -1 ma 2.5-3.6v 2.2 ? v v ol output low voltage i ol = 0.1 ma 1.65-2.2v ? 0.2 v i ol = 2.1 ma 2.5-3.6v ? 0.4 v v ih input high voltage 1.65-2.2v 1.4 v dd + 0.2 v 2.5-3.6v 2.2 v dd + 0.3 v v il (1) input low voltage 1.65-2.2v ?0.2 0.4 v 2.5-3.6v ?0.2 0.6 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a notes: 1. v il (min.) = ?1.0v for pulse width less than 10 ns. absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.2 to v dd +0.3 v t bias temperature under bias ?40 to +85 c v dd v dd related to gnd ?0.2 to +3.8 v t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? ac test conditions parameter 62wv51216all 62wv51216bll (unit) (unit) input pulse level 0.4v to v dd -0.2 0.4v to v dd -0.3v input rise and fall times 5 ns 5ns input and output timing v ref v ref and reference level output load see figures 1 and 2 see figures 1 and 2 ac test loads figure 1 figure 2 62wv51216all 62wv51216bll (1.65v - 2.2v) (2.5v - 3.6v) r1( ?) 3070 1029 r2( ?) 3150 1728 v ref 0.9v 1.5v v tm 1.8v 2.8v capacitance (1) symbol parameter conditions max. unit c in input capacitance v in = 0v 8 pf c out input/output capacitance v out = 0v 10 pf note: 1. tested initially and after any design or process changes that may affect these parameters. r1 5 pf including jig and scope r2 output vtm r1 30 pf including jig and scope r2 output vtm
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? IS62WV51216ALL, power supply characteristics (1) (over operating range) symbol parameter test conditions max. unit 70 i cc v dd dynamic operating v dd = max., com. 20 ma supply current i out = 0 ma, f = f max ind. 25 i cc 1 operating supply v dd = max., cs1 = 0.2v com. 4 ma current we = v dd ? 0.2v ind. 4 cs2 = v dd ? 0.2v, f = 1 mhz i sb 1 ttl standby current v dd = max., com. 0.3 ma (ttl inputs) v in = v ih or v il ind. 0.3 cs1 = v ih , cs2 = v il , f = 1 mh z or ulb control v dd = max., v in = v ih or v il cs1 = v il , f = 0, ub = v ih , lb = v ih i sb 2 cmos standby v dd = max., com. 15 a current (cmos inputs) cs1 v dd ? 0.2v, ind. 21 cs2 0.2v, typ. (1) 3 v in v dd ? 0.2v, or v in 0.2v, f = 0 or ulb control v dd = max., cs1 = v il , cs2=v ih v in v dd ? 0.2v, or v in 0.2v, f = 0; ub / lb = v dd ? 0.2v note: . 1. typical values are measured at v dd = 1.8v, t a = 25 o c and not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? is62wv51216bll, power supply characteristics (1) (over operating range) symbol parameter test conditions max. max. max. unit 45 55 70 i cc v dd dynamic operating v dd = max., com. 35 30 25 ma supply current i out = 0 ma, f = f max ind. 40 35 30 i cc 1 operating supply v dd = max., cs1 = 0.2v com. 5 5 5 ma current we = v dd ? 0.2v ind. 5 5 5 cs2 = v dd ? 0.2v, f = 1 mhz i sb 1 ttl standby current v dd = max., com. 0.3 0.3 0.3 ma (ttl inputs) v in = v ih or v il ind. 0.3 0.3 0.3 cs1 = v ih , cs2 = v il , f = 1 mh z or ulb control v dd = max., v in = v ih or v il cs1 = v il , f = 0, ub = v ih , lb = v ih i sb 2 cmos standby v dd = max., com. 20 20 20 a current (cmos inputs) cs1 v dd ? 0.2v, ind. 25 25 25 cs2 0.2v, typ. (2) 444 v in v dd ? 0.2v, or v in 0.2v, f = 0 or ulb control v dd = max., cs1 = v il , cs2=v ih v in v dd ? 0.2v, or v in 0.2v, f = 0; ub / lb = v dd ? 0.2v note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested.
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? data valid previous data valid t aa t oha t oha t rc d out address ac waveforms read cycle no. 1 (1,2) (address controlled) ( cs1 = oe = v il , cs2 = we = v ih , ub or lb = v il ) read cycle switching characteristics (1) (over operating range) 45 ns 55 ns 70 ns symbol parameter min. max. mi n. max. min. max. unit t rc read cycle time 45 ? 55 ? 70 ? ns t aa address access time ? 45 ? 55 ? 70 ns t oha output hold time 10 ? 10 ? 10 ? ns t acs1/ t acs2 cs1/ cs2 access time ? 45 ? 55 ? 70 ns t doe oe access time ? 20 ? 25 ? 35 ns t hzoe (2) oe to high-z output ? 15 ? 20 ? 25 ns t lzoe (2) oe to low-z output 5 ? 5 ? 5 ? ns t hzcs1/ t hzcs2 (2) cs1/ cs2 to high-z output 0 15 0 20 0 25 ns t lzcs1/ t lzcs2 (2) cs1/ cs2 to low-z output 10 ? 10 ? 10 ? ns t ba lb , ub access time ? 45 ? 55 ? 70 ns t hzb lb , ub to high-z output 0 15 0 20 0 25 ns t lzb lb , ub to low-z output 0 ? 0 ? 0 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0 .4 to v dd -0.2v/0.4v to v dd -0.3v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? t rc t oha t aa t doe t lzoe t ace1/ t ace2 t lzce1/ t lzce2 t hzoe high-z data valid t hzcs1/ t hzcs2 address oe cs1 cs2 dout lb , ub t hzb t ba t lzb ac waveforms read cycle no. 2 (1,3) ( cs1 , cs2, oe , and ub / lb controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , cs1 , ub , or lb = v il . cs2= we =v ih . 3. address is valid prior to or coincident with cs1 low transition.
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? notes: 1. write is an internally generated signal asserted during an overlap of the low states on the cs1 , cs2 and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = ( cs1 ) [ ( lb ) = ( ub ) ] ( we ). ac waveforms write cycle no. 1 (1,2) ( cs1 controlled, oe = high or low) data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 cs2 we dout din lb , ub t pwb write cycle switching characteristics (1,2) (over operating range) 45ns 55 ns 70 ns symbol parameter min. max. min. max. min. max. unit t wc write cycle time 45 ? 55 ? 70 ? ns t scs1/ t scs2 cs1/ cs2 to write end 35 ? 45 ? 60 ? ns t aw address setup time to write end 35 ? 45 ? 60 ? ns t ha address hold from write end 0 ? 0 ? 0 ? ns t sa address setup time 0 ? 0 ? 0 ? ns t pwb lb , ub valid to end of write 35 ? 45 ? 60 ? ns t pwe (4) we pulse width 35 ? 40 ? 50 ? ns t sd data setup to write end 20 ? 25 ? 30 ? ns t hd data hold from write end 0 ? 0 ? 0 ? ns t hzwe (3) we low to high-z output ? 20 ? 20 ? 30 ns t lzwe (3) we high to low-z output 5 ? 5 ? 5 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4 to v dd -0.2v/0.4v to v dd -0.3v and output loading specified in figure 1. 2. the internal write time is defined by the overlap of cs1 low, cs2 high and ub or lb , and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that termi nates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 4. t pwe > t hzwe + t sd when oe is low.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? write cycle no. 2 ( we controlled: oe is high during write cycle) write cycle no. 3 ( we controlled: oe is low during write cycle) data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb , ub dout din data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb , ub dout din
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? write cycle no. 4 ( ub / lb controlled) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 t hd t sa t hzwe address cs1 ub , lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha ub_cswr4.eps high cs2
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? data retention waveform ( cs1 controlled) v dd cs1 v dd - 0.2v t sdr t rdr v dr cs1 gnd 1.65v 1.4v data retention mode data retention switching characteristics symbol p arameter test condition min. max. unit v dr v dd for data retention see data retention waveform 1.2 3.6 v i dr data retention current v dd = 1.2v, cs1 v dd ? 0.2v ? 20 a t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns data retention waveform (cs2 controlled) v dd cs2 0.2v t sdr t rdr v dr 0.4v ce2 gnd 3.0 2.2v data retention mode
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? is62wv51216bll (2.5v - 3.6v) commercial range: 0c to +70c speed (ns) order part no. package 45 is62wv51216bll-45b mini bga (7.2mm x 8.7mm) 55 is62wv51216bll-55t tsop-ii is62wv51216bll-55b mini bga (7.2mm x 8.7mm) 70 is62wv51216bll-70t tsop-ii industrial range: ?40c to +85c speed (ns) order part no. package 55 is62wv51216bll-55ti tsop-ii is62wv51216bll-55bi mini bga (7.2mm x 8.7mm) 70 is62wv51216bll-70ti tsop-ii is62wv51216bll-70bi mini bga (7.2mm x 8.7mm) is62wv51216bll-70xi die ordering information IS62WV51216ALL (1.65v - 2.2v) commercial range: 0c to +70c speed (ns) order part no. package 70 IS62WV51216ALL-70t tsop-ii IS62WV51216ALL-70b mini bga (7.2mm x 8.7mm) industrial range: ?40c to +85c speed (ns) order part no. package 70 IS62WV51216ALL-70ti tsop-ii IS62WV51216ALL-70bi mini bga (7.2mm x 8.7mm) IS62WV51216ALL-70xi die
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 rev. a 02/07/03 IS62WV51216ALL, is62wv51216bll issi ? mini ball grid array package code: b (48-pin) notes: 1. controlling dimensions are in millimeters. seating plane a a1 a2 a b c d e f g h e e d1 e1 e d b (48x) top view bottom view 6 5 4 3 2 1 1 2 3 4 5 6 a b c d e f g h mbga - 7.2mm x 8.7mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a ? ? 1.20 ? ? 0.047 a1 0 .24 ? 0.30 0.009 ? 0.012 a2 0.60 ? ? 0.024 ? ? d 8.60 8.70 8.80 0.339 0.343 0.346 d1 5.25bsc 0.207bsc e 7.10 7.20 7.30 0.280 0.283 0.287 e1 3.75bsc 0.148bsc e 0.75bsc 0.030bsc b 0.30 0.35 0.40 0.012 0.014 0.016
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. e 02/20/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. plastic tsop package code: t (type ii) d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t - type ii) millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max ref. std. no. leads (n) 32 44 50 a ? 1.20 ? 0.047 ? 1.20 ? 0.047 ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 d 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 e1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 bsc 0.050 bsc 0.80 bsc 0.032 bsc 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 zd 0.95 ref. 0.037 ref. 0.81 ref. 0.032 ref. 0.88 ref. 0.035 ref 0 5 0 5 0 5 0 5 0 5 0 5

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